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fn6692 rev 3.00 page 1 of 16 june 5, 2015 fn6692 rev 3.00 june 5, 2015 isl80020, isl80020 a, ISL80015, ISL80015a compact synchronous buck converters datasheet the isl80020 , isl80020a , ISL80015 and ISL80015a are highly efficient, monolithic, synchronous step-down dc/dc converters that can deliver up to 2a of cont inuous output current from a 2.7v to 5.5v input supply. they use peak current mode control architecture to allow very low duty cycle operation. they operate at either 1mhz or 2mhz switching frequency, thereby providing superior transient response and allowing for the use of small inductors. they have excellent stability. the isl80020, isl80020a, ISL80015 and ISL80015a integrate very low r ds(on) mosfets in order to maximize efficiency. in addition, since the high-side mosf et is a pmos, the need for a boot capacitor is eliminated, thereby reducing external component count. they can operate at 100% duty cycle (at 1mhz). the device is configured in pwm (pulse width modulation) for fast transient response, which helps reduce the output noise and rf interference. these devices are offered in a space saving 8 pin 2mmx2mm tdfn lead free package with exposed pad for improved thermal performance. the complete converter occupies less than 64mm 2 area. related literature ug026 , ?isl800xxxdemo1z demonstration boards user guide? features ?v in range 2.7v to 5.5v ?i out maximum is 1.5a or 2a (see table 1 on page 2 ) ? switching frequency is 1mhz or 2mhz (see table 1 on page 2 ) ? overcurrent and short circuit protection ? over-temperature/thermal protection ? negative current protection ? power-good and enable ? 100% duty cycle (1mhz) ? internal soft-start and soft-stop ?v in undervoltage lockout and v out overvoltage protection ? up to 95% peak efficiency applications ? general purpose pol ? industrial, instrumentation, and medical equipment ? telecom and networking equipment ?game console figure 1. typical application circuit configuration figure 2. efficiency vs load, f sw = 2mhz, v in = 5v, t a = +25c r 1 r 2 v o vfb ------------ 1 C ?? ?? = (eq. 1) vin en sgnd pg phase fb pgnd nc 1 3 2 4 8 6 7 5 vout l1 c1 22f c2 gnd vin gnd en pg ISL80015, isl80020 epad 9 +2.7v...+5.5v +1.8v/2a 22f 100k 1% 0.6v c3 22pf r2 r1 200k 1% 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 efficiency (%) output load (a) 1.8v out 1.5v out 2.5v out 3.3v out
isl80020, isl80020a, ISL80015, ISL80015a fn6692 rev 3.00 page 2 of 16 june 5, 2015 table 1. summary of key differences part# i out (max) (a) f sw (mhz) v in range (v) v out range (v) package size ISL80015 1.5 1 2.7 to 5.5 0.6 to 5.5 8 pin 2mmx2mm tdfn ISL80015a 1.5 2 isl80020 2 1 isl80020a 2 2 note: in this datasheet, the parts listed in the table are collectively called ?device?. table 2. component value selection table v out (v) c1 (f) c2 (f) c3 (pf) l1 (h) r1 (k ) r2 (k ) 0.8 22 22 22 1.0~2.2 33 100 1.2 22 22 22 1.0~2.2 100 100 1.5 22 22 22 1.0~2.2 150 100 1.8 22 22 22 1.0~3.3 200 100 2.5 22 22 22 1.5~3.3 316 100 3.3 22 22 22 1.5~4.7 450 100
isl80020, isl80020a, ISL80015, ISL80015a fn6692 rev 3.00 page 3 of 16 june 5, 2015 pin configuration isl80020, isl80020a, ISL80015, ISL80015a (8 ld 2x2 tdfn) top view pad 1 3 4 vin sgnd fb 2 nc pgnd pg en 7 5 6 8 phase epad pin 9 (gnd) pin descriptions pin # pin name pin description 1 vin the input supply for the power stage of the pwm regulator an d the source for the internal linear regulator that provides bias for the ic. place a minimum of 10f ceramic capacitance from vin to gnd and as close as possible to the ic for decoupling. 2 en device enable input. when the voltage on this pin rises abov e 1.4v, the device is enabled. the device is disabled when the pin is pulled to ground. when the device is disabled, a 100 resistor discharges the ou tput through the phase pin. see figure 3 , ? functional block diagram ? on page 4 for details. 3sgndconnect pin 3 to epad 4 pg power-good output is pulled to ground during the soft-start interval and also when the output voltage is below regulation limits. there is an internal 5m internal pull-up resistor on this pin. 5 fb feedback pin for the regulator. fb is the negative input to the voltage loop error amplifier. the output voltage is set by an external resistor divider connected to fb. in addition, the power-good pwm regulator?s power-good and undervoltage protection circuits use fb to monitor the output voltage. 6 nc connect nc pin to epad 7 pgnd power and analog ground connections. connect directly to the board ground plane. 8 phase power stage switching node for output voltage regulation. co nnect to the output inductor. this pin is discharged by an 100 resistor when the device is disabled. see figure 3 , ? functional block diagram ? on page 4 for details. 9 e pad the exposed pad must be connected to the pgnd pin for pr oper electrical performance. pl ace as many vias as possible under the pad connecting to the pgnd plane for optimal thermal performance.
isl80020, isl80020a, ISL80015, ISL80015a fn6692 rev 3.00 page 4 of 16 june 5, 2015 functional block diagram figure 3. functional block diagram phase + csa ocp + + slope comp slope soft start soft- eamp comp pwm logic controller protection hs driver fb 0.85*vref pg shutdown vin pgnd scp 0.3v en shutdown 1ms delay 27pf 200k 3pf 6k -- 100 shutdown vref + neg current sensing p n uv 1.15*vref 5m vin bandgap oscillator ov + + + + + - - - - + -
isl80020, isl80020a, ISL80015, ISL80015a fn6692 rev 3.00 page 5 of 16 june 5, 2015 ordering information part number ( notes 1 , 2 , 3 ) tape and reel quantity part marking technical specifications temp. range (c) package tape and reel (rohs compliant) pkg. dwg. # isl80020irz-t 1000 020 2a, 1mhz -40 to +85 8 ld tdfn l8.2x2c isl80020irz-t7a 250 020 2a, 1mhz -40 to +85 8 ld tdfn l8.2x2c isl80020airz-t 1000 20a 2a, 2mhz -40 to +85 8 ld tdfn l8.2x2c isl80020airz-t7a 250 20a 2a, 2mhz -40 to +85 8 ld tdfn l8.2x2c ISL80015irz-t 1000 015 1.5a, 1mhz -40 to +85 8 ld tdfn l8.2x2c ISL80015irz-t7a 250 015 1.5a, 1mhz -40 to +85 8 ld tdfn l8.2x2c ISL80015airz-t 1000 a15 1.5a, 2mhz -40 to +85 8 ld tdfn l8.2x2c ISL80015airz-t7a 250 a15 1.5a, 2mhz -40 to +85 8 ld tdfn l8.2x2c isl80020frz-t 1000 20f 2a, 1mhz -40 to +125 8 ld tdfn l8.2x2c isl80020frz-t7a 250 20f 2a, 1mhz -40 to +125 8 ld tdfn l8.2x2c isl80020afrz-t 1000 0af 2a, 2mhz -40 to +125 8 ld tdfn l8.2x2c isl80020afrz-t7a 250 0af 2a, 2mhz -40 to +125 8 ld tdfn l8.2x2c ISL80015frz-t 1000 15f 1.5a, 1mhz -40 to +125 8 ld tdfn l8.2x2c ISL80015frz-t7a 250 15f 1.5a, 1mhz -40 to +125 8 ld tdfn l8.2x2c ISL80015afrz-t 1000 5af 1.5a, 2mhz -40 to +125 8 ld tdfn l8.2x2c ISL80015afrz-t7a 250 5af 1.5a, 2mhz -40 to +125 8 ld tdfn l8.2x2c notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl80020 , isl80020a , ISL80015 , ISL80015a . for more information on msl please see techbrief tb363 .
isl80020, isl80020a, ISL80015, ISL80015a fn6692 rev 3.00 page 6 of 16 june 5, 2015 absolute maximum rating s thermal information vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v (dc) or 7v (20ms) phase . . . . . . . . . . . . . . -1.5v (100ns)/-0.3v (dc) to 6v (dc) or 7v (20ms) en, pg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vin + 0.3v fb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v junction temperature range at 0a . . . . . . . . . . . . . . . . . . . . . . . . . .+150c esd rating human body model (tested per jesd22-js-001) . . . . . . . . . . . . . . . . 4kv machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 300v charged device model (tested per jesd22-c101d) . . . . . . . . . . . . . 2kv latch-up (tested per jesd78d, class 2, level a) . . . 100ma at +125c thermal resistance (typical, notes 4 , 5 ) ? ja (c/w) ? jc (c/w) 2x2 tdfn package . . . . . . . . . . . . . . . . . . . 71 7 maximum junction temperature (plastic package) . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c operating junction temperature range . . . . . . . . . . . . . .-40c to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions vin supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v load current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 2a temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications t a = -40c to +125c, v in = 2.7v to 5.5v, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the junction operating temperature range, -40c to +125c. parameter symbol test conditions min ( note 6 )typ max ( note 6 )units input supply v in undervoltage lockout threshold v uvlo rising, no load 2.5 2.7 v falling, no load 2.2 2.4 v quiescent supply current i vin f sw = 1mhz, no load at the output 7 15 ma f sw = 2mhz, no load at the output 10 22 ma shutdown supply current i sd v in = 5.5v, en = low 1.2 10 a output regulation feedback voltage v fb 0.594 0.600 0.606 v t a = -40c to +125c 0.589 0.606 v vfb bias current i vfb v fb = 2.7v, t a = -40c to +125c -350 50 350 na line regulation v in = v o + 0.5v to 5.5v (nominal 3.6v) t a = -40c to +125c -0.32 -0.05 0.28 %/v load regulation see ( note 7 ) < -0.2 %/a soft-start ramp time cycle ( note 7 ) 1ms protections positive peak current limit iplimit 2a application (v in = 3.6v) 2.8 3.18 3.6 a 1.5a application (v in = 3.6v) 2.1 2.5 2.9 a thermal shutdown temperature rising 150 c thermal shutdown hysteresis ( note 7 ) temperature falling 25 c compensation error amplifier transconductance ( note 7 ) 40 a/v transresistance rt 0.24 0.3 0.40 phase p-channel mosfet on-resistance v in = 5v, i o = 200ma 117 m n-channel mosfet on-resistance v in = 5v, i o = 200ma 86 m
isl80020, isl80020a, ISL80015, ISL80015a fn6692 rev 3.00 page 7 of 16 june 5, 2015 oscillator nominal switching frequency f sw isl80020, ISL80015 800 1000 1200 khz isl80020a, ISL80015a 1640 2000 2360 khz pg output low voltage 1ma sinking current 0.3 v delay time (rising edge) 0.5 1 2.5 ms pgood delay time (falling edge) 5s pg pin leakage current pg = v in 0.01 0.1 a ovp pg rising threshold 110 115 125 % ovp pg hysteresis 2% uvp pg rising threshold 80 85 90 % uvp pg hysteresis 5% en logic logic input low 0.4 v logic input high 1.4 v logic input leakage current i en pulled up to 5.5v 0.1 1 a notes: 6. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. 7. not tested in production. characteri zed using evaluation board. refer to figures 8 through 11 load regulation diagrams. +105c t a represents near worst case operating point. electrical specifications t a = -40c to +125c, v in = 2.7v to 5.5v, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the junction operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )units
isl80020, isl80020a, ISL80015, ISL80015a fn6692 rev 3.00 page 8 of 16 june 5, 2015 typical performance curves figure 4. efficiency vs load, f sw = 1mhz, v in = 3.3v, t a = +25c figure 5. efficiency vs load, f sw = 2mhz, v in = 3.3v, t a = +25c figure 6. efficiency vs load, f sw = 1mhz, v in = 5v, t a = +25c figure 7. efficiency vs load, f sw = 2mhz, v in = 5v, t a = +25c figure 8. v out regulation vs load, f sw = 2mhz, v out = 1.5v, t a = +25c figure 9. v out regulation vs load, f sw = 2mhz, v out = 1.8v, t a = +25c 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 output load (a) efficiency (%) 1.8v out 1.5v out 2.5v out 1.2v out 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 efficiency (%) output load (a) 1.8v out 1.5v out 1.2v out 2.5v out 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 output load (a) efficiency (%) 1.8v out 1.5v out 3.3v out 2.5v out 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 efficiency (%) output load (a) 1.8v out 1.5v out 2.5v out 3.3v out 1.490 1.495 1.500 1.505 1.510 1.515 1.520 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 output voltage (v) output load (a) 5v in 3.3v in 1.780 1.785 1.790 1.795 1.800 1.805 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 o u t p u t v o l t a g e ( v ) output load (a) 1.810 3.3v in 5v in
isl80020, isl80020a, ISL80015, ISL80015a fn6692 rev 3.00 page 9 of 16 june 5, 2015 figure 10. v out regulation vs load, f sw = 2mhz, v out = 2.5v, t a = +25c figure 11. v out regulation vs load, f sw = 2mhz, v out = 3.3v, t a = +25c figure 12. start-up at no load, f sw = 2mhz, v in = 5v, t a = +25c figure 13. shutdown at no load, f sw = 2mhz, v in = 5v, t a = +25c figure 14. start-up at 2a load, f sw = 2mhz, v in = 5v, t a = +25c figure 15. shutdown at 2a load, f sw = 2mhz, v in = 5v, t a = +25c typical performance curves (continued) 2.475 2.480 2.485 2.490 2.495 2.500 2.505 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 output load (a) output voltage (v) 3.3v in pwm 5v in pwm 3.305 3.310 3.315 3.320 3.325 3.330 3.335 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 output load (a) output voltage (v) 5v in phase 5v/div v out 1v/div ven 2v/div pg 5v/div 1ms/div 1ms/div phase 5v/div v out 1v/div ven 2v/div pg 5v/div phase 5v/div v out 1v/div ven 2v/div pg 5v/div 1ms/div phase 5v/div v out 1v/div ven 2v/div pg 5v/div 1ms/div
isl80020, isl80020a, ISL80015, ISL80015a fn6692 rev 3.00 page 10 of 16 june 5, 2015 figure 16. start-up at 1.5a load, f sw = 2mhz, v in = 5v, t a = +25c figure 17. shutdown at 1.5a load, f sw = 2mhz, v in = 5v, t a = +25c figure 18. start-up v in at 2a load, f sw = 2mhz, v in = 5v, t a = +25c figure 19. shutdown v in at 2a load, f sw = 2mhz, v in = 5v, t a = +25c figure 20. jitter at no load, f sw = 2mhz, v in = 5v, t a = +25c figure 21. jitter at full load, f sw = 2mhz, v in = 5v, t a = +25c typical performance curves (continued) ven 5v/div v out 1v/div i l 1a/div pg 5v/div 1ms/div ven 5v/div v out 1v/div i l 1a/div pg 5v/div 1ms/div 500s/div v in 5v/div v out 1v/div i l 1a/div pg 5v/div 1ms/div v in 5v/div v out 1v/div i l 1a/div pg 5v/div 10ns/div phase 1v/div 10ns/div phase 1v/div
isl80020, isl80020a, ISL80015, ISL80015a fn6692 rev 3.00 page 11 of 16 june 5, 2015 figure 22. steady state at no load, f sw = 2mhz, v in = 5v, t a = +25c figure 23. load transient, f sw = 2mhz, v in = 5v, t a = +25c figure 24. overcurrent protection, f sw = 2mhz, v in = 5v, t a = +25c figure 25. over-temperature protection, f sw = 2mhz, v in =5v, t a = +163c typical performance curves (continued) 500ns/div phase 5v/div v out 10mv/div i l 0.5a/div 200s/div v out ripple 50mv/div i l 1a/div 500s/div v out 0.5v/div i l 1a/div pg 5v/div 1ms/div v out 0.5v/div pg 2v/div
isl80020, isl80020a, ISL80015, ISL80015a fn6692 rev 3.00 page 12 of 16 june 5, 2015 theory of operation the device is a step-down switching regulator optimized for battery powered applications. it operates at a high switching frequency (1mhz or 2mhz), which enables the use of smaller inductors resulting in small form factor, while also providing excellent efficiency. the quiescent current is typically only 1.2a when the regulator is shut down. pwm control scheme the device employs the current-mode pulse-width modulation (pwm) control scheme for fast transient response and pulse-by-pulse curre nt limiting. see ? functional block diagram ? on page 4 . the current loop consists of the oscillator, the pwm comparator, current sensing circuit and the slope compensation for the current loop stability. the slope compensation is 900mv/ts, which changes with frequency. the gain for the current sensing circuit is typically 300mv/a. the control reference for the current loops comes from the error amplifier's (eamp) output. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp-up. when the sum of the current amplifier cs a and the slope compensation reaches the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-fet and turn on the n-channel mosfet. the n-fet stays on until the end of the pwm cycle. figure 26 shows the typical operating waveforms during the pwm operatio n. the dotted lines illustrate the sum of the slope compensati on ramp and the current-sense amplifier?s csa output. the reference voltage is 0.6v, which is used by feedback to adjust the output of the error amplifier, veamp. the error amplifier is a trans conductanc e amplifier that converts the voltage error signal to a current output. the voltage loop is internally compensated with the 27pf and 200k rc network. the maximum eamp voltage output is precisely clamped to 1.6v. overcurrent protection the overcurrent protection is realized by monitoring the csa output with the ocp comparator, as shown in the ? functional block diagram ? on page 4 . the current sensing circuit has a gain of 300mv/a, from the p-fet current to the csa output. when the csa output reaches a threshold, the ocp comparator is tripped to turn off the p-fet immediately. th e overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper mosfet. upon detection of overcurrent condition, the upper mosfet will be immediately turned off and will not be turned on again until the next switching cycle. if the overcurrent condition goes away, the output will resume back into regulation point. short-circuit protection the short-circuit protection (scp) comparator monitors the vfb pin voltage for output short-circ uit protection. when the vfb is lower than 0.3v, the scp compar ator forces the pwm oscillator frequency to drop to 1/3 of the normal operation value. this comparator is effective during star t-up or an output short-circuit event. negative current protection similar to the overcurrent, the negative current protection is realized by monitoring the current across the low-side n-fet, as shown in the ? functional block diagram ? on page 4 . when the valley point of the inductor current reaches -1.5a for 2 consecutive cycles, both p-fet and n-fet shut off. the 100 in parallel to the n-fet will activate discharging the output into regulation. the control will begin to switch when output is within regulation. pg pg is an output of a window comp arator that continuously monitors the buck regulator output voltage. pg is actively held low when en is low and during the buck regulator soft-start period. after 1ms delay of the soft-start period, pg beco mes high impedance as-long-as the output voltage is within nominal regulation voltage set by vfb. when vfb drops 15% below or raises 15% above the nominal regulation voltage, the device pulls pg low. any fault condition forces pg low until the fault condition is cleared by attempts to soft-start. there is an internal 5m pull-up resistor to fit most applications. an external resistor can be added from pg to vin for more pull-up strength. uvlo when the input voltage is below th e undervoltage lock-out (uvlo) threshold, the regulator is disabled. enable, disable and soft start-up after the vin pin exceeds its rising por trip point (nominal 2.5v), the device begins operation. if the en pin is held low externally, nothing happens until this pin is released. once the en is released and above the logic th reshold, the internal default soft-start time is 1ms. discharge mode (soft-stop) when a transition to shutdown mode occurs or the vin uvlo is set, the outputs discharge to gnd through an internal 100 switch. thermal shutdown the device has built-in thermal protection. when the internal temperature reaches +150c, the regulator is completely shutdown. as the temperature drops to +125c, the device resume operation by stepping through the soft-start. figure 26. pwm operation waveforms v eamp v csa duty cycle i l v out
isl80020, isl80020a, ISL80015, ISL80015a fn6692 rev 3.00 page 13 of 16 june 5, 2015 power derating characteristics to prevent the device from ex ceeding the maximum junction temperature, some thermal analysis is required. the temperature rise is given by equation 2 : where pd is the power dissipated by the regulator and ja is the thermal resistance from the junc tion of the die to the ambient temperature. the junction temperature, t j , is given by equation 3 : where t a is the ambient temperature. for the dfn package, the ja is +71c/w. the actual junction temperature should not exceed the absolute maximum junction temperature of +125c when considering the thermal design. the device delivers full current at ambient temperatures up to +85c if the thermal impedance from the thermal pad maintains the junction temperat ure below the thermal shutdown level, depending on the input voltage/output voltage combination and the switching frequency. the device power dissipation must be reduced to maintain the junction temperature at or below th e thermal shutdown level. figure 27 illustrates the approximate output current derating curve versus ambient temperature for the isl80020eval1z kit. applications information output inductor and capacitor selection to consider steady state and transient operations, the isl80020a and ISL80015a typically requires a 1.2h, while the isl80020 and ISL80015 typically requires a 2.2h output inductor. higher or lower inductor values can be used to optimize the total converter system performance. for example, for higher output voltage 3.3v application, in order to decrease the inductor ripple current and output voltage ripple, the output inductor value can be increased. it is recommended to set the inductor ripple current to be approximately 30% of the maximum output current for optimized performance. the inductor ripple current can be expressed as shown in equation 4 : the inductor?s saturation current rating needs to be at least larger than the peak current. the device uses an internal compensation network and the output capacitor value is dependent on the output voltage. the ceramic capacitor is recommended to be x5r or x7r. output voltage selection the output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. the output voltage programming resistor, r 1 , will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. the value for the feedback resistor is typically between 10k and 100k ?? as shown in equation 5 . if the output voltage desired is 0.6v, then r 2 is left unpopulated and r 1 is shorted. there is a leakage current from vin to phase. it is recommended to preload the output with 10a minimum. for better performance, add 22pf in parallel with r 1 ?? input capacitor selection the main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. at least two 22f x5r or x7r ceramic capacitors are a good starting point for th e input capacitor selection. output capacitor selection an output capacitor is required to filter the inductor current. output ripple voltage and transi ent response ar e two critical factors when considering output capacitance choice. the current mode control loop allows for the usage of low esr ceramic capacitors and thus smaller bo ard layout. electrolytic and polymer capacitors may also be used. additional consideration applies to ceramic capacitors. while they offer excellent overall performance and reliability, the actual in-circuit capacitance must be considered. ceramic capacitors are rated using large peak-to-peak voltage swings and with no dc bias. in the dc/dc converter applic ation, these cond itions do not reflect reality. as a result, the actual capacitance may be considerably lower than the advertised value. consult the manufacturers datasheet to determine the actual in-application capacitance. most manufacturers publish capacitance vs dc bias so this effect can be easily accommodated. the effects of ac voltage are not frequently published, but an assumption of ~20% further reduction will generally suffice. the result of these considerations can easily result in an effective capacitance 50% lower than the rated value. nonetheless, they are a very good t rise pd ??? ja ?? = (eq. 2) t j t a t rise + ?? = (eq. 3) 0 0.5 1.0 1.5 2.0 2.5 50 60 70 80 90 100 110 120 130 1v 1.5v 2.5v 3.3v temperature (c) output current (v) v in = 5v, olfm figure 27. derating curve vs temperature ? i v o 1 v o v in --------- C ?? ?? ?? ? lf sw ? -------------------------------------- - = (eq. 4) r 1 r 2 v o vfb ------------ 1 C ?? ?? = (eq. 5)
isl80020, isl80020a, ISL80015, ISL80015a fn6692 rev 3.00 page 14 of 16 june 5, 2015 choice in many applications due to their reliability and extremely low esr. equations 6 and 7 allow calculation of the required capacitance to meet a desired ripple voltage level. additional capacitance may be used. for the ceramic capacitors (low esr) = where ? i is the inductor?s peak-to-peak ripple current, f sw is the switching frequency and c out is the output capacitor. if using electrolytic capacitors then: regarding transient response needs, a good starting point is to determine the allowable overshoot in v out if the load is suddenly removed. in this case, energy stored in the inductor will be transferred to c out causing its voltage to rise. after calculating capacitance required for both ripple and transient needs, choose the larger of the calculated values. equation 8 determines the required output capacitor value in order to achieve a desired overshoot relative to the regulated voltage. where v outmax /v out is the relative maximum overshoot allowed during the removal of the load. for an overshoot of 5%, the equation becomes equation 9 : layout considerations the pcb layout is a very important converter design step to make sure the designed converter works well. the power loop is composed of the output inductor l?s, the output capacitor c out , the phase?s pins and the pgnd pin. it is necessary to make the power loop as small as possibl e and the connecting traces among them should be direct, short and wide. the switching node of the converter, the phase pins and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. the input capacitor should be placed as closely as possible to the vin pin and the ground of the input and output capacitors should be connected as closely as possible. the heat of the ic is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for better emi performance. it is recommended to add at least 4 vias ground connection within the pad for the best thermal relief. v outripple ? i 8 ? f sw ? c out ------------------------------------ - = (eq. 6) v outripple ? i*esr = (eq. 7) (eq. 8) c out i out 2 * l v out 2 * v outmax v out ? ?? 2 1 ? C --------------------------------------------------------------- ----------------------------- = c out i out 2 * l v out 2 * 1.05 ? 2 1 ? C ----------------------------------------------------- = (eq. 9)
fn6692 rev 3.00 page 15 of 16 june 5, 2015 isl80020, isl80020a, ISL80015, ISL80015a intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2015. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change june 5, 2015 fn6692.3 added related literature on page 1. -thermal information table on page 6: updated: -junction temperature range: -55c to +125c to maximum junction temperature (plastic package): +150c added: -ambient temperature range: -40c to +125c -operating junction temperature range: -40c to +125c -recommended operating conditions on page 6 updated from ?junction temperature range: -40c to +125c? to ?temperature: -40c to +125c -electrical specifications on page 6: in heading: -changed temperature range, from -40c to +85c to: -40c to +125c. -changed from: ?tj = -40c to +125c to: ?ta = -40c to +125c. under output regulation section for test condition updated: -feedback voltage from: ?tj = -40c to +125c? to ?ta = -40c to +125c?. -vfb bias current from ?vfb = 2.7v, tj = -40c to +125c? to ?vfb = 2.7v, ta = -40c to +125c?. -line regulation from ?tj = -40c to +125c? to ?ta = -40c to +125c?. - pod l8.2x2c updated from rev 0 to rev 1. changes since rev 0: tiebar note updated from: tiebar shown (if present) is a non-functional feature. to: tiebar shown (if present) is a non-functional feat ure and may be located on any of the 4 sides (or ends). april 1, 2015 fn6692.2 under ?theory of operation? on page 12, changed typical value from ?5a? to ?1.2a?. under ?enable, disable and soft start-up? on page 12, changed typical value from ?2.7v? to ?2.5v?. february 17, 2015 fn6692.1 changed min value of vfb bias current in electrical spec table from -120 to -350. february 5, 2015 fn6692.0 initial release
isl80020, isl80020a, ISL80015, ISL80015a fn6692 rev 3.00 page 16 of 16 june 5, 2015 package outline drawing l8.2x2c 8 lead thin dual flat no-lead plastic package (tdfn) with e-pad rev 1, 5/15 located within the zone indicate d. the pin #1 identifier may be unless otherwise specified, t olerance : decimal 0.05 the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 2.00 2.00 ( 6x0.50 ) 2.00 2.00 ( 8x0.30 ) ( 8x0.20 ) ( 8x0.30 ) 0.50 0.800.050 exp.dap 0.25 1.450.050 exp.dap ( 8x0.25 ) 0.80 1.45 pin #1 index area b 0.10 m a c 0 . 75 ( 0 . 80 max) c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. 0 . 05 max. 0 . 2 ref c 6 index area pin 1 6 (4x) 0.15 a b 1 package outline 8 tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).

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